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hvdc-control

HVDC control and protection systems delivered with converter stations

Hitachi Energy MACH, Siemens Energy HVDC, GE Vernova HVDC

SystemTechniques · 14Primitives · 40 hvdc-control Clock synchronizationdistributed · medium: Estimate a clock's offset from four timestamps, filter out queueing noise, and steer the clock smoothly; NTP gets about a millisecond, PTP with hardware timestamps under a microsecond.›Alarm managementembedded · medium: Turn raw process limits into a few actionable operator alarms with delay, deadband, acknowledge and shelving states, plus flood measurement.›Fault detection isolation recoveryembedded · medium: Monitor/response tables, fault isolation and safe-mode recovery hierarchies for autonomous systemsHot-standby redundancyembedded · medium: A second, always-current controller shadows the primary and takes over within a few cycles of silence; epochs stop the old primary from fighting back.›Industrial network segmentationembedded · medium: Zones and conduits (IEC 62443/Purdue) with firewalls and protocol allow-lists for OTModular multilevel converter controlembedded · medium: Submodule capacitor balancing and nearest-level modulation for modular multilevel convertersSafety monitor architectureembedded · medium: Independent doer/checker safety monitor that forces a safe state when the main channel misbehavesPID controllerrobotics · low: Drive a measured value to a setpoint with three terms on the error: proportional, integral, derivative. The default feedback loop for motors, heaters, drones and gimbals.›Phase-locked loop (digital)signal-processing · low: Feedback loop that locks a local oscillator to the phase and frequency of an input tone; the core of carrier recovery, clock recovery and GNSS tracking.›Hierarchical state machinesystems · low: Nest states so a substate inherits its parent's reactions and only overrides what differs, with ordered entry and exit actions along the path.›Redundancy votingembedded · low: N-modular redundancy and MooN voting (2oo3, TMR) with discrepancy detectionWatchdog timerembedded · low: A hardware down-counter that resets the chip unless software proves, in time and in a plausible pattern, that it is still healthy.›Fixed-rate control loopembedded · low: Run a controller at an exact period using absolute deadlines and a fixed dt, so jitter never accumulates and the math stays valid.›PWM generationembedded · low: A timer's counter, period and compare registers draw the pulse train; preload, dead time and DMA make duty changes glitch-free, shoot-through-free and cheap.›Dnp3 protocolembedded · low: DNP3 outstation/master protocol: event buffers, unsolicited reporting, time-stamped dataDroop controlembedded · low: Frequency/voltage droop: proportional power response that lets inverters share load without communicationGate drive desat protectionembedded · low: Detect IGBT/MOSFET short circuit by watching Vce/Vds while on (desaturation), blank briefly, then soft turn-off and latch a faultReal time fieldbusembedded · low: Deterministic cyclic fieldbuses (EtherCAT, PROFINET IRT): on-the-fly frames, distributed clocksSynchrophasor estimationembedded · low: GPS-timed DFT phasor, frequency and ROCOF estimation in PMUsDeterministic fixed-point mathgame-networking · low: Bit-identical simulation math across CPUs, compilers and builds: integer fixed-point formats, the float traps (FMA, x87, fast-math, libm), deterministic trig, sqrt and RNG.›IIR and FIR filterssignal-processing · low: Two ways to shape a sampled signal's spectrum: FIR (finite taps, always stable, exact linear phase) or IIR (feedback, a few coefficients, cheap but phase-distorting).›Robust statisticsstatistics · low: Location and scale estimates (median, MAD, trimmed mean, Huber M-estimator) that stay correct when a minority of the data is garbage.›Debouncing throttlingsystems · low: Coalescing rapid events: debounce (wait for quiet), throttle (max rate), and cancelling stale in-flight requests+ 7 more techniques+ 24 more primitives

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