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solar-inverter

grid-tied solar inverter with monitoring

SMA, SolarEdge, Enphase

SystemTechniques · 19Primitives · 73 solar-inverter Deterministic simulation testingdistributed · medium: Run the whole system in one thread under a seeded scheduler with simulated network, disk and clock, so every failure replays from its seed.›Primary-backup replicationdistributed · medium: One node orders all writes and ships them to standbys; the acknowledgement rule (none, one, all) sets what a crash loses, and an external arbiter decides who takes over.›A/B partition updatesembedded · medium: Two bootable slots and a small atomic metadata block: write the new image to the idle slot, try it once, and fall back by itself unless it reports healthy.›Anti islanding detectionembedded · medium: Detect loss of grid with passive voltage/frequency windows and active frequency or impedance shift, then trip within required timeFault detection isolation recoveryembedded · medium: Monitor/response tables, fault isolation and safe-mode recovery hierarchies for autonomous systemsSafety-critical coding standardsembedded · medium: Which rule sets (MISRA C, CERT C, JPL Power of Ten, Rust lint subsets) apply when software must not fail, what they forbid, and how to enforce them in CI.›Safety monitor architectureembedded · medium: Independent doer/checker safety monitor that forces a safe state when the main channel misbehavesWatchdog timerembedded · low: A hardware down-counter that resets the chip unless software proves, in time and in a plausible pattern, that it is still healthy.›Maximum power point trackingcontrol · low: Hunt the PV maximum power point by perturb-and-observe or incremental conductance adjusting the operating voltageHdr histogramdata-structures · low: Log-linear bucketed histograms with bounded relative error for latency percentilesCan bus framingembedded · low: CAN / CAN FD frames, bitwise arbitration, bit stuffing, CRC and error confinementDma transfersembedded · low: DMA controllers: descriptors, circular buffers, cache coherence for zero-CPU data movementDroop controlembedded · low: Frequency/voltage droop: proportional power response that lets inverters share load without communicationFixed-rate control loopembedded · low: Run a controller at an exact period using absolute deadlines and a fixed dt, so jitter never accumulates and the math stays valid.›Gate drive desat protectionembedded · low: Detect IGBT/MOSFET short circuit by watching Vce/Vds while on (desaturation), blank briefly, then soft turn-off and latch a faultModbus protocolembedded · low: Modbus RTU/TCP registers and function codes with polling and CRCPWM generationembedded · low: A timer's counter, period and compare registers draw the pulse train; preload, dead time and DMA make duty changes glitch-free, shoot-through-free and cheap.›Rms power metering dspembedded · low: Sample voltage and current to compute RMS, active/reactive power and energy accumulationDeterministic fixed-point mathgame-networking · low: Bit-identical simulation math across CPUs, compilers and builds: integer fixed-point formats, the float traps (FMA, x87, fast-math, libm), deterministic trig, sqrt and RNG.›Interrupt handlinghardware-os · low: How a device signal reaches a CPU handler through an interrupt controller and vector table, and how top/bottom halves, polling switch-over and coalescing keep load bounded.›Process supervisionhardware-os · low: A parent process starts services, reaps their exits and restarts them under a delay and burst-limit policy, then stops them with SIGTERM before SIGKILL.›Mqtt protocolnetworking · low: MQTT pub/sub: topics, QoS 0/1/2, retained messages, sessions and keepalivePID controllerrobotics · low: Drive a measured value to a setpoint with three terms on the error: proportional, integral, derivative. The default feedback loop for motors, heaters, drones and gimbals.›+ 12 more techniques+ 57 more primitives

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