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nat-gateway

carrier-grade NAT gateway

CGNAT

SystemTechniques · 0Primitives · 19 nat-gateway Cuckoo hashingdata-structures · low: Every key lives in one of two candidate buckets, so lookups read at most two cache lines; inserts evict residents to their alternate bucket.›Connection trackingnetworking · low: Per-flow state table (5-tuple, TCP state, timeouts) for stateful packet handlingEcmpnetworking · low: Equal-cost multipath: hash flows across next hops; resilient hashing on changesInternet checksumnetworking · low: Ones-complement IP/TCP/UDP checksum, incremental update (RFC 1624) and offloadIpfix flow exportnetworking · low: IPFIX/NetFlow template-based flow record export and collectionKernel-bypass networkingnetworking · low: User space (DPDK, AF_XDP) or an in-driver eBPF hook (XDP) handles packets straight from NIC rings, skipping sockets, for 10-40 Mpps per core.›Network address translationnetworking · low: NAT mapping tables, endpoint-independent mapping/filtering, hairpinning and port allocationPort block allocationnetworking · low: Allocate port blocks per subscriber in CGNAT to cut logging volumeReceive side scalingnetworking · low: NIC hashing of flows to RX queues (RSS) and symmetric hashing for per-core processingHierarchical timing wheelsystems · low: Timers bucketed by expiry into wheels of slots, coarser wheels for far deadlines: O(1) insert and cancel for millions of timeouts.›False sharingconcurrency · low: Independent variables written by different cores on one cache line force the line to bounce between cores; pad or regroup hot data to fix it.›Memory orderingconcurrency · low: What Relaxed, Acquire, Release and SeqCst atomics actually guarantee, what they cost on x86 and ARM, and which one each pattern needs.›Fast hash functionsdata-structures · low: Non-cryptographic hashes built from 64×64→128-bit multiplies and xor-shifts; pick by key size, trust level and whether the hash is persisted.›SPSC ring bufferdata-structures · low: Bounded wait-free queue for exactly one producer and one consumer thread, built from an array and two indices with acquire/release ordering.›CPU caches and the memory hierarchyhardware-os · low: Sizes, line widths and latencies of L1/L2/L3/DRAM on modern x86 and Apple M-series, and the data-layout rules that follow from them.›Huge pageshardware-os · low: 2 MB/1 GB pages to cut TLB misses; THP vs explicit hugetlbfs+ 3 more primitives

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