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gpu-driver

GPU driver stack

Mesa

SystemTechniques · 5Primitives · 26 gpu-driver Instruction schedulingcompilers · medium: List scheduling over dependence DAGs with latency models; software pipelining of loopsInstruction selectioncompilers · medium: Cover the IR with target instruction patterns at least cost; greedy maximal munch is simple, dynamic programming over a tree or DAG is optimal.›Register allocationcompilers · medium: Map unlimited virtual registers onto a few machine registers, spilling the rest to the stack; linear scan is fast, graph coloring and splitting allocators give better code.›Dataflow analysiscompilers · medium: Compute a fact per program point (live variables, reaching definitions, available expressions) by iterating transfer functions over the CFG to a fixed point.›Graph coloringgraphs · medium: Greedy/DSatur colouring for conflict-free assignment such as radio channelsSSA formcompilers · low: Give every variable exactly one definition, merging at joins with phi functions; def-use becomes explicit and optimizations turn sparse and cheap.›Shared memory ipcconcurrency · low: Shared memory rings and futex signalling between processesSPSC ring bufferdata-structures · low: Bounded wait-free queue for exactly one producer and one consumer thread, built from an array and two indices with acquire/release ordering.›Display scanout modesettinggraphics · low: KMS: CRTCs, planes, atomic commits, page flips, vblank events and direct scanoutGPU command buffersgraphics · low: Record GPU work as a flat list of commands on the CPU, submit it in batches, and reuse its memory through a ring of frames in flight guarded by fences.›Gpu synchronization fencesgraphics · low: Fences, timeline semaphores and sync files between GPU queues, CPU and processesPipeline state cachinggraphics · low: Cache compiled shader pipelines across runs, precompile permutations, avoid hitchesTexture tiling swizzlinggraphics · low: Tiled and swizzled GPU image layouts and address computationDMA and IOMMUhardware-os · low: How devices move data by direct memory access, and how an IOMMU gives each device its own address space, faults on stray accesses and lets user space or guests own a device safely.›Gpu priority preemptionhardware-os · low: GPU context priorities and compute or graphics preemption granularity for latency-critical workInterrupt handlinghardware-os · low: How a device signal reaches a CPU handler through an interrupt controller and vector table, and how top/bottom halves, polling switch-over and coalescing keep load bounded.›System call interfacehardware-os · low: The controlled gate between user code and the kernel: number and arguments in registers, a trap instruction, a validated handler, a result or error code.›Buddy allocatorsystems · low: Power-of-two block splitting and coalescing; base of kernel page and GPU heap allocatorsd-ary heapdata-structures · low: Array heap with d children per node (d = 4 typical): half the binary heap's depth, siblings in one cache line, faster priority queues.›Topological sortgraphs · low: Order the vertices of a DAG so every edge points forward; the core of build systems, schedulers and dependency resolution, with cycle detection for free.›Instruction pipelininghardware-os · low: Pipeline stages, hazards, forwarding and stalls in CPU cores+ 10 more primitives

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