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cuda-platform

GPU programming platform

NVIDIA CUDA toolkit, AMD ROCm/HIP, Intel oneAPI

SystemTechniques · 11Primitives · 37 cuda-platform Alias analysiscompilers · medium: Decide whether two pointers may refer to the same memory (Andersen, Steensgaard, type-based) to enable optimizationsDataflow analysiscompilers · medium: Compute a fact per program point (live variables, reaching definitions, available expressions) by iterating transfer functions over the CFG to a fixed point.›Debug info (DWARF)compilers · medium: DWARF stores a tree of typed entries (DIEs), a line-number bytecode, unwind tables and location expressions that map machine state back to source; pick it for ELF/Mach-O debug builds.›Function inliningcompilers · medium: Inline call sites by cost model and call-graph order; enables downstream optimizationsInstruction schedulingcompilers · medium: List scheduling over dependence DAGs with latency models; software pipelining of loopsInstruction selectioncompilers · medium: Cover the IR with target instruction patterns at least cost; greedy maximal munch is simple, dynamic programming over a tree or DAG is optimal.›Linking and relocationcompilers · medium: The linker merges object files, matches each undefined name to one definition, assigns addresses and patches every recorded reference (relocation); dynamic linking defers part of that to load time.›SSA formcompilers · low: Give every variable exactly one definition, merging at joins with phi functions; def-use becomes explicit and optimizations turn sparse and cheap.›Machine code emissioncompilers · low: Encode instructions to bytes for x86-64 and AArch64, branch relaxation, constant poolsDominator treecompilers · low: Dominators via Lengauer-Tarjan or Cooper-Harvey-Kennedy; dominance frontiers for SSACalling conventions abicompilers · low: System V, Windows x64 and AAPCS64 ABIs: argument registers, stack frames, struct passing, FFIRecursive-descent parsingcompilers · low: Hand-written top-down parser with one function per grammar rule; simple, fast, with full control over error messages and recovery.›Shared memory ipcconcurrency · low: Shared memory rings and futex signalling between processesGPU command buffersgraphics · low: Record GPU work as a flat list of commands on the CPU, submit it in batches, and reuse its memory through a ring of frames in flight guarded by fences.›Gpu synchronization fencesgraphics · low: Fences, timeline semaphores and sync files between GPU queues, CPU and processesPipeline state cachinggraphics · low: Cache compiled shader pipelines across runs, precompile permutations, avoid hitchesDMA and IOMMUhardware-os · low: How devices move data by direct memory access, and how an IOMMU gives each device its own address space, faults on stray accesses and lets user space or guests own a device safely.›Gpu priority preemptionhardware-os · low: GPU context priorities and compute or graphics preemption granularity for latency-critical workSimt warp schedulinghardware-os · low: SIMT execution: warps, divergence, occupancy and latency hiding on GPU SMsSystem call interfacehardware-os · low: The controlled gate between user code and the kernel: number and arguments in registers, a trap instruction, a validated handler, a result or error code.›Virtual memory and the TLBhardware-os · low: How page tables and TLBs translate every address, what TLB reach means, and when 2 MiB or 1 GiB huge pages pay off on Linux.›Collective communicationml-training · low: The family of group exchanges (broadcast, reduce, all-gather, reduce-scatter, all-to-all) and the latency-plus-bytes cost model that picks ring, tree or direct algorithms by message size and topology.›Kernel fusionml-training · low: Merge chains of memory-bound GPU ops into one kernel, so intermediates stay in registers instead of round-tripping through HBM.›+ 4 more techniques+ 21 more primitives

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