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Embedded and IoT
rtos
embedded real-time OS
FreeRTOS, Zephyr
System
Techniques · 0
Primitives · 17
rtos
Counting semaphore
concurrency · low: Counting and binary semaphores for task signalling and resource counting
Memory ordering
concurrency · low: What Relaxed, Acquire, Release and SeqCst atomics actually guarantee, what they cost on x86 and ARM, and which one each pattern needs.
›
MPMC bounded queue
concurrency · low: Vyukov's array queue for many producers and consumers: each slot carries a sequence number, so one CAS per operation claims a slot without locks.
›
Priority inheritance
concurrency · low: Priority inheritance/ceiling mutexes preventing unbounded priority inversion
SPSC ring buffer
data-structures · low: Bounded wait-free queue for exactly one producer and one consumer thread, built from an array and two indices with acquire/release ordering.
›
Earliest deadline first
embedded · low: Dynamic-priority EDF scheduling: optimal on one CPU up to 100 % utilization
Memory protection unit
embedded · low: A handful of base/size regions with permissions, checked on every access by the CPU, give microcontroller tasks isolation and stack-overflow traps without an MMU.
›
Preemptive priority scheduling
embedded · low: Always run the highest-priority ready task, switching the instant a higher one becomes ready; selection is O(1) with one FIFO per priority and a bitmap.
›
Rate monotonic analysis
embedded · low: Schedulability tests and response-time analysis for periodic real-time tasks
Watchdog timer
embedded · low: A hardware down-counter that resets the chip unless software proves, in time and in a plausible pattern, that it is still healthy.
›
Context switching
hardware-os · low: Handing a core to another task by saving and loading registers, stack and address space; the hidden cache and TLB cost outweighs the direct one.
›
Interrupt handling
hardware-os · low: How a device signal reaches a CPU handler through an interrupt controller and vector table, and how top/bottom halves, polling switch-over and coalescing keep load bounded.
›
Tickless idle
hardware-os · low: Suppress the periodic tick while idle and compensate time on wake to save power
Hierarchical timing wheel
systems · low: Timers bucketed by expiry into wheels of slots, coarser wheels for far deadlines: O(1) insert and cancel for millions of timeouts.
›
Slab allocator
systems · low: Pre-carve pages into equal-size slots per size class with an in-place free list: O(1) alloc and free, no external fragmentation, cache-warm reuse.
›
False sharing
concurrency · low: Independent variables written by different cores on one cache line force the line to bounce between cores; pad or regroup hot data to fix it.
›
+ 1 more primitives
System
Techniques · 0
Primitives · 17
rtos
Counting semaphore
concurrency · low: Counting and binary semaphores for task signalling and resource counting
Memory ordering
concurrency · low: What Relaxed, Acquire, Release and SeqCst atomics actually guarantee, what they cost on x86 and ARM, and which one each pattern needs.
›
MPMC bounded queue
concurrency · low: Vyukov's array queue for many producers and consumers: each slot carries a sequence number, so one CAS per operation claims a slot without locks.
›
Priority inheritance
concurrency · low: Priority inheritance/ceiling mutexes preventing unbounded priority inversion
SPSC ring buffer
data-structures · low: Bounded wait-free queue for exactly one producer and one consumer thread, built from an array and two indices with acquire/release ordering.
›
Earliest deadline first
embedded · low: Dynamic-priority EDF scheduling: optimal on one CPU up to 100 % utilization
Memory protection unit
embedded · low: A handful of base/size regions with permissions, checked on every access by the CPU, give microcontroller tasks isolation and stack-overflow traps without an MMU.
›
Preemptive priority scheduling
embedded · low: Always run the highest-priority ready task, switching the instant a higher one becomes ready; selection is O(1) with one FIFO per priority and a bitmap.
›
Rate monotonic analysis
embedded · low: Schedulability tests and response-time analysis for periodic real-time tasks
Watchdog timer
embedded · low: A hardware down-counter that resets the chip unless software proves, in time and in a plausible pattern, that it is still healthy.
›
Context switching
hardware-os · low: Handing a core to another task by saving and loading registers, stack and address space; the hidden cache and TLB cost outweighs the direct one.
›
Interrupt handling
hardware-os · low: How a device signal reaches a CPU handler through an interrupt controller and vector table, and how top/bottom halves, polling switch-over and coalescing keep load bounded.
›
Tickless idle
hardware-os · low: Suppress the periodic tick while idle and compensate time on wake to save power
Hierarchical timing wheel
systems · low: Timers bucketed by expiry into wheels of slots, coarser wheels for far deadlines: O(1) insert and cancel for millions of timeouts.
›
Slab allocator
systems · low: Pre-carve pages into equal-size slots per size class with an in-place free list: O(1) alloc and free, no external fragmentation, cache-warm reuse.
›
False sharing
concurrency · low: Independent variables written by different cores on one cache line force the line to bounce between cores; pad or regroup hot data to fix it.
›
CPU caches and the memory hierarchy
hardware-os · low: Sizes, line widths and latencies of L1/L2/L3/DRAM on modern x86 and Apple M-series, and the data-layout rules that follow from them.
›
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