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Hardware and datacenter
gpu
GPU architecture
NVIDIA H100, Blackwell
System
Techniques · 1
Primitives · 17
gpu
Cache coherence protocols
hardware-os · medium: MESI and MOESI, snooping vs directories: how cores keep caches consistent and what that costs
CPU caches and the memory hierarchy
hardware-os · low: Sizes, line widths and latencies of L1/L2/L3/DRAM on modern x86 and Apple M-series, and the data-layout rules that follow from them.
›
Network on chip
hardware-os · low: On-chip mesh and ring interconnects: routers, virtual channels, deadlock-free routing
Mipmapping texture filtering
graphics · low: Mip pyramids, trilinear and anisotropic filtering, LOD selection from derivatives
Triangle rasterization
graphics · low: Triangle setup, edge functions, depth buffering for viewport rendering
Dram organization
hardware-os · low: Channels, ranks, banks, rows; row-buffer hits, refresh, timing parameters; DDR5 and HBM
Gpu memory coalescing banking
hardware-os · low: Coalesced global loads, shared memory bank conflicts, L2 and HBM bandwidth on GPUs
Power management dvfs
hardware-os · low: DVFS governors, P- and C-states, race-to-idle, thermal throttling
Roofline model
hardware-os · low: Bound a kernel's speed by min(peak FLOP/s, arithmetic intensity × memory bandwidth) to know whether to optimize compute or data movement.
›
Simt warp scheduling
hardware-os · low: SIMT execution: warps, divergence, occupancy and latency hiding on GPU SMs
Systolic matrix units
hardware-os · low: Systolic arrays and tensor cores: dataflow of operands, tile shapes, accumulator precision
Tiled matrix multiplication
ml-training · low: Block GEMM into tiles held in shared memory and registers, so each byte loaded from DRAM feeds many FMAs; the core of fast GEMM.
›
Low precision number formats
numerics · low: Bf16, fp16, fp8 (E4M3, E5M2), MX block formats and int4: ranges, rounding, scaling
Bounding volume hierarchy
physics · low: Binary tree of nested bounding boxes; prunes overlap and ray queries to O(log n) for any size distribution, and supports cheap insert/remove for moving objects.
›
Hamming codes
signal-processing · low: Hamming and SECDED block codes for single-error correction in links and memory
Memory ordering
concurrency · low: What Relaxed, Acquire, Release and SeqCst atomics actually guarantee, what they cost on x86 and ARM, and which one each pattern needs.
›
SIMD programming
hardware-os · low: Process 4-16 lanes per instruction with AVX2, AVX-512 or NEON via Rust std::arch, with runtime dispatch and a portable fallback.
›
+ 1 more primitives
System
Techniques · 1
Primitives · 17
gpu
Cache coherence protocols
hardware-os · medium: MESI and MOESI, snooping vs directories: how cores keep caches consistent and what that costs
CPU caches and the memory hierarchy
hardware-os · low: Sizes, line widths and latencies of L1/L2/L3/DRAM on modern x86 and Apple M-series, and the data-layout rules that follow from them.
›
Network on chip
hardware-os · low: On-chip mesh and ring interconnects: routers, virtual channels, deadlock-free routing
Mipmapping texture filtering
graphics · low: Mip pyramids, trilinear and anisotropic filtering, LOD selection from derivatives
Triangle rasterization
graphics · low: Triangle setup, edge functions, depth buffering for viewport rendering
Dram organization
hardware-os · low: Channels, ranks, banks, rows; row-buffer hits, refresh, timing parameters; DDR5 and HBM
Gpu memory coalescing banking
hardware-os · low: Coalesced global loads, shared memory bank conflicts, L2 and HBM bandwidth on GPUs
Power management dvfs
hardware-os · low: DVFS governors, P- and C-states, race-to-idle, thermal throttling
Roofline model
hardware-os · low: Bound a kernel's speed by min(peak FLOP/s, arithmetic intensity × memory bandwidth) to know whether to optimize compute or data movement.
›
Simt warp scheduling
hardware-os · low: SIMT execution: warps, divergence, occupancy and latency hiding on GPU SMs
Systolic matrix units
hardware-os · low: Systolic arrays and tensor cores: dataflow of operands, tile shapes, accumulator precision
Tiled matrix multiplication
ml-training · low: Block GEMM into tiles held in shared memory and registers, so each byte loaded from DRAM feeds many FMAs; the core of fast GEMM.
›
Low precision number formats
numerics · low: Bf16, fp16, fp8 (E4M3, E5M2), MX block formats and int4: ranges, rounding, scaling
Bounding volume hierarchy
physics · low: Binary tree of nested bounding boxes; prunes overlap and ray queries to O(log n) for any size distribution, and supports cheap insert/remove for moving objects.
›
Hamming codes
signal-processing · low: Hamming and SECDED block codes for single-error correction in links and memory
Memory ordering
concurrency · low: What Relaxed, Acquire, Release and SeqCst atomics actually guarantee, what they cost on x86 and ARM, and which one each pattern needs.
›
SIMD programming
hardware-os · low: Process 4-16 lanes per instruction with AVX2, AVX-512 or NEON via Rust std::arch, with runtime dispatch and a portable fallback.
›
CUDA and GPU languages
languages · low: Programming GPUs: thousands of lockstep threads, bound by memory bandwidth; libraries first, Triton for fused kernels, CUDA C++ for peak speed.
›
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