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dram-hbm
DRAM and HBM memory devices
SK hynix HBM3E, Samsung DDR5, Micron
System
Techniques · 8
Primitives · 17
dram-hbm
Event driven logic simulation
hardware-os · medium: RTL and gate simulation with event wheels, delta cycles and 4-state logic
Row hammer mitigation
hardware-os · medium: Counter DRAM disturbance from repeated row activations: sampled or counted aggressor tracking with targeted neighbour refresh (TRR, RFM)
Static timing analysis
hardware-os · medium: Propagate latest/earliest arrival forward and required times backward through a DAG; slack = required - arrival, and the minimum-slack path is the critical one.
›
Modified nodal analysis
numerics · medium: Build circuit equations from netlists by element stamps (MNA), including voltage sources
Critical path analysis
graphs · medium: Longest dependency chain in a DAG of timed spans or build actions
Sparse direct solver
numerics · medium: Solve sparse Ax = b exactly by reordering, symbolic analysis, numeric LLᵀ/LU and triangular solves; fill-in, not flops per entry, decides the cost.
›
Fill-reducing ordering
numerics · medium: Permute a sparse symmetric matrix before Cholesky/LU so the factor has few new nonzeros; minimum degree, nested dissection and RCM trade quality, speed and parallelism.
›
Edac memory scrubbing
embedded · low: ECC/EDAC memory with periodic scrubbing to correct radiation-induced bit flips
Memory self test march
embedded · low: March RAM tests, ROM CRCs and CPU self-tests required by safety standards
Dram organization
hardware-os · low: Channels, ranks, banks, rows; row-buffer hits, refresh, timing parameters; DDR5 and HBM
Dram training
hardware-os · low: Memory init at boot: SPD read, timing and voltage training, read/write leveling
Adaptive equalization
signal-processing · low: LMS/RLS equalizer filters that invert channel distortion from training or decisions
Hamming codes
signal-processing · low: Hamming and SECDED block codes for single-error correction in links and memory
Phase-locked loop (digital)
signal-processing · low: Feedback loop that locks a local oscillator to the phase and frequency of an input tone; the core of carrier recovery, clock recovery and GNSS tracking.
›
d-ary heap
data-structures · low: Array heap with d children per node (d = 4 typical): half the binary heap's depth, siblings in one cache line, faster priority queues.
›
Hierarchical timing wheel
systems · low: Timers bucketed by expiry into wheels of slots, coarser wheels for far deadlines: O(1) insert and cancel for millions of timeouts.
›
Topological sort
graphs · low: Order the vertices of a DAG so every edge points forward; the core of build systems, schedulers and dependency resolution, with cycle detection for free.
›
Newton root finding
numerics · low: Linearize at the guess and jump to the tangent root; quadratic convergence near a simple root, made robust by brackets (1D) or line search.
›
Sparse matrices (CSR)
numerics · low: Compressed sparse row stores only nonzeros as row pointers, column indices and values; SpMV streams them once, so it is memory-bandwidth bound.
›
Stiff solvers (implicit, BDF)
numerics · low: Implicit steps solve a small nonlinear system so fast decaying modes stay stable at any step size; BDF methods are the stiff-ODE workhorse.
›
BFS and DFS
graphs · low: The two basic graph traversals; BFS gives hop distances and levels, DFS gives discovery/finish order for cycles, components and topological order.
›
LU and Cholesky factorization
numerics · low: Factor A = PLU (any square matrix, partial pivoting) or A = LLᵀ (SPD) once in O(n³), then solve each right-hand side in O(n²).
›
PRNGs (PCG, xoshiro)
numerics · low: Small, fast, statistically strong non-cryptographic generators: PCG32 and xoshiro256**, with seeding, parallel streams and unbiased ranges.
›
+ 1 more techniques
+ 1 more primitives
System
Techniques · 8
Primitives · 17
dram-hbm
Event driven logic simulation
hardware-os · medium: RTL and gate simulation with event wheels, delta cycles and 4-state logic
Row hammer mitigation
hardware-os · medium: Counter DRAM disturbance from repeated row activations: sampled or counted aggressor tracking with targeted neighbour refresh (TRR, RFM)
Static timing analysis
hardware-os · medium: Propagate latest/earliest arrival forward and required times backward through a DAG; slack = required - arrival, and the minimum-slack path is the critical one.
›
Modified nodal analysis
numerics · medium: Build circuit equations from netlists by element stamps (MNA), including voltage sources
Critical path analysis
graphs · medium: Longest dependency chain in a DAG of timed spans or build actions
Sparse direct solver
numerics · medium: Solve sparse Ax = b exactly by reordering, symbolic analysis, numeric LLᵀ/LU and triangular solves; fill-in, not flops per entry, decides the cost.
›
Fill-reducing ordering
numerics · medium: Permute a sparse symmetric matrix before Cholesky/LU so the factor has few new nonzeros; minimum degree, nested dissection and RCM trade quality, speed and parallelism.
›
Graph partitioning
graphs · medium: Split a graph into k balanced parts with few edges between them; multilevel coarsen-partition-refine (METIS, KaHIP) for quality, streaming heuristics (LDG, Fennel) for one-pass scale.
›
Edac memory scrubbing
embedded · low: ECC/EDAC memory with periodic scrubbing to correct radiation-induced bit flips
Memory self test march
embedded · low: March RAM tests, ROM CRCs and CPU self-tests required by safety standards
Dram organization
hardware-os · low: Channels, ranks, banks, rows; row-buffer hits, refresh, timing parameters; DDR5 and HBM
Dram training
hardware-os · low: Memory init at boot: SPD read, timing and voltage training, read/write leveling
Adaptive equalization
signal-processing · low: LMS/RLS equalizer filters that invert channel distortion from training or decisions
Hamming codes
signal-processing · low: Hamming and SECDED block codes for single-error correction in links and memory
Phase-locked loop (digital)
signal-processing · low: Feedback loop that locks a local oscillator to the phase and frequency of an input tone; the core of carrier recovery, clock recovery and GNSS tracking.
›
d-ary heap
data-structures · low: Array heap with d children per node (d = 4 typical): half the binary heap's depth, siblings in one cache line, faster priority queues.
›
Hierarchical timing wheel
systems · low: Timers bucketed by expiry into wheels of slots, coarser wheels for far deadlines: O(1) insert and cancel for millions of timeouts.
›
Topological sort
graphs · low: Order the vertices of a DAG so every edge points forward; the core of build systems, schedulers and dependency resolution, with cycle detection for free.
›
Newton root finding
numerics · low: Linearize at the guess and jump to the tangent root; quadratic convergence near a simple root, made robust by brackets (1D) or line search.
›
Sparse matrices (CSR)
numerics · low: Compressed sparse row stores only nonzeros as row pointers, column indices and values; SpMV streams them once, so it is memory-bandwidth bound.
›
Stiff solvers (implicit, BDF)
numerics · low: Implicit steps solve a small nonlinear system so fast decaying modes stay stable at any step size; BDF methods are the stiff-ODE workhorse.
›
BFS and DFS
graphs · low: The two basic graph traversals; BFS gives hop distances and levels, DFS gives discovery/finish order for cycles, components and topological order.
›
LU and Cholesky factorization
numerics · low: Factor A = PLU (any square matrix, partial pivoting) or A = LLᵀ (SPD) once in O(n³), then solve each right-hand side in O(n²).
›
PRNGs (PCG, xoshiro)
numerics · low: Small, fast, statistically strong non-cryptographic generators: PCG32 and xoshiro256**, with seeding, parallel streams and unbiased ranges.
›
Slab allocator
systems · low: Pre-carve pages into equal-size slots per size class with an in-place free list: O(1) alloc and free, no external fragmentation, cache-warm reuse.
›
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