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cpu-core

out-of-order CPU core

Apple M-series, AMD Zen

SystemTechniques · 2Primitives · 15 cpu-core Cache coherence protocolshardware-os · medium: MESI and MOESI, snooping vs directories: how cores keep caches consistent and what that costsTomasulo out of orderhardware-os · medium: Register renaming, reservation stations and reorder buffer for out-of-order executionMemory orderingconcurrency · low: What Relaxed, Acquire, Release and SeqCst atomics actually guarantee, what they cost on x86 and ARM, and which one each pattern needs.›CPU caches and the memory hierarchyhardware-os · low: Sizes, line widths and latencies of L1/L2/L3/DRAM on modern x86 and Apple M-series, and the data-layout rules that follow from them.›Branch predictionhardware-os · low: How CPUs guess branch outcomes, what a misprediction costs, and when to replace branches with conditional moves, masks or sorted data.›Instruction decode uop cachehardware-os · low: Instruction fetch, decoders, micro-op cache, macro-fusion and front-end bottlenecksInstruction pipelininghardware-os · low: Pipeline stages, hazards, forwarding and stalls in CPU coresLoad store queue disambiguationhardware-os · low: Load and store queues, store forwarding, memory dependence predictionArithmetic circuitshardware-os · low: Adder and multiplier circuits: carry-lookahead, prefix adders, Booth encoding, Wallace and Dadda treesDram organizationhardware-os · low: Channels, ranks, banks, rows; row-buffer hits, refresh, timing parameters; DDR5 and HBMHardware prefetchinghardware-os · low: Stride, stream and spatial prefetchers; software prefetch hints and when they helpPower management dvfshardware-os · low: DVFS governors, P- and C-states, race-to-idle, thermal throttlingSIMD programminghardware-os · low: Process 4-16 lanes per instruction with AVX2, AVX-512 or NEON via Rust std::arch, with runtime dispatch and a portable fallback.›Virtual memory and the TLBhardware-os · low: How page tables and TLBs translate every address, what TLB reach means, and when 2 MiB or 1 GiB huge pages pay off on Linux.›Floating-point errornumerics · low: How IEEE 754 rounding error accumulates and how to contain it: compensated (Kahan/Neumaier) and pairwise summation, error-free transformations with FMA, ULP comparisons.›Microarchitectural side channelssecurity · low: Cache timing (Prime+Probe, Flush+Reload) and speculative-execution (Spectre, Meltdown) leaks and their mitigationsNetwork on chiphardware-os · low: On-chip mesh and ring interconnects: routers, virtual channels, deadlock-free routing

In-house systems

Named systems of this kind at large companies, with their paper or write-up.

GravitonAmazon