Hardware & OS
What the machine really does: caches, SIMD, virtual memory, the page cache, durable writes and zero-allocation I/O.
CPU
Where the nanoseconds go.
CPU caches and the memory hierarchy
lowSizes, line widths and latencies of L1/L2/L3/DRAM on modern x86 and Apple M-series, and the data-layout rules that follow from them.
Roofline model
lowBound a kernel's speed by min(peak FLOP/s, arithmetic intensity × memory bandwidth) to know whether to optimize compute or data movement.
SIMD programming
lowProcess 4-16 lanes per instruction with AVX2, AVX-512 or NEON via Rust std::arch, with runtime dispatch and a portable fallback.
Branch prediction
lowHow CPUs guess branch outcomes, what a misprediction costs, and when to replace branches with conditional moves, masks or sorted data.
instruction pipelining
Planned.
tomasulo out of order
Planned.
load store queue disambiguation
Planned.
instruction decode uop cache
Planned.
hardware prefetching
Planned.
cache coherence protocols
Planned.
Structure of arrays and hot/cold splitting
lowStore each field in its own array and keep rarely used fields apart, so a loop reads only the bytes it needs and the compiler can vectorize it.
vliw static scheduling
Planned.
Memory
Virtual memory and mapping files.
Virtual memory and the TLB
lowHow page tables and TLBs translate every address, what TLB reach means, and when 2 MiB or 1 GiB huge pages pay off on Linux.
mmap and the page cache
lowHow read() and mmap reach file data through the kernel page cache, what readahead and madvise do, and why databases use their own buffer pool instead.
huge pages
Planned.
numa aware allocation
Planned.
dram organization
Planned.
Copy-on-write fork
lowfork() gives the child the parent's whole address space by sharing pages read-only and copying one only when someone writes it; vfork and posix_spawn skip even that.
memory pressure reclaim
Planned.
Storage I/O
Getting bytes onto disk durably and fast.
fsync, O_DSYNC and O_DIRECT
lowWhat fsync, fdatasync, O_DSYNC, O_DIRECT and F_FULLFSYNC really guarantee on Linux and macOS, and the exact call sequences for crash-safe files.
SSD and NVMe internals
lowNAND pages and erase blocks, the FTL, garbage collection and write amplification, NVMe queues and queue depth, and 4 KiB alignment, with the numbers that matter.
CRC32C checksums
lowThe Castagnoli CRC-32 with dedicated instructions on x86 (SSE4.2) and ARMv8. It is the standard fast integrity check for storage blocks, logs and network frames.
atomic file replacement
Planned.
advisory file locking
Planned.
File system watching
lowTreat OS change notices as hints, debounce them, and rescan and diff a snapshot whenever notices overflow or may be lost.
block io multiqueue
Planned.
io request scheduling
Planned.
nvme queues
Planned.
nvme over fabrics
Planned.
overlay filesystem
Planned.
fuse userspace filesystem
Planned.
Buffers
I/O without allocating.
Kernel mechanisms
System calls, interrupts, CPU scheduling and in-kernel extension points.
System call interface
lowThe controlled gate between user code and the kernel: number and arguments in registers, a trap instruction, a validated handler, a result or error code.
Context switching
lowHanding a core to another task by saving and loading registers, stack and address space; the hidden cache and TLB cost outweighs the direct one.
Interrupt handling
lowHow a device signal reaches a CPU handler through an interrupt controller and vector table, and how top/bottom halves, polling switch-over and coalescing keep load bounded.
cpu scheduling eevdf
Planned.
heterogeneous core scheduling
Planned.
ebpf
Planned.
live kernel patching
Planned.
capability ipc
Planned.
library os
Planned.
tickless idle
Planned.
power management dvfs
Planned.
unix socket fd passing
Planned.
Processes & terminals
Spawning, supervising, confining and accounting for processes.
Process supervision
lowA parent process starts services, reaps their exits and restarts them under a delay and burst-limit policy, then stops them with SIGTERM before SIGKILL.
pseudo terminals
Planned.
ptrace process control
Planned.
crash signal handling
Planned.
Cgroups and namespaces
lowLinux namespaces limit what a process can see; cgroup v2 limits and accounts what it may use. Containers, sandboxes and job schedulers are built from the two.
resource usage accounting
Planned.
cpu isolation and pinning
Planned.
Checkpoint and restart
mediumPeriodically save enough state to resume a computation after a crash, preemption or move, with an interval that balances save cost against lost work.
mobile background execution
Planned.
Performance analysis
Measuring where time goes on real hardware.
hardware performance counters
Planned.
sampling profiling pmu
Planned.
benchmarking methodology
Planned.
dynamic instrumentation probes
Planned.
flame graphs
Planned.
instrumented profiling
Planned.
Virtualization
Running guests: hardware virtualization, paravirtual devices, migration and snapshots.
hardware virtualization kvm
Planned.
nested paging ept
Planned.
virtio devices
Planned.
memory ballooning
Planned.
memory live migration
Planned.
dirty page tracking
Planned.
vm snapshot restore
Planned.
DMA and IOMMU
lowHow devices move data by direct memory access, and how an IOMMU gives each device its own address space, faults on stray accesses and lets user space or guests own a device safely.
gpu virtualization
Planned.
Boot & firmware
From reset vector to running OS, and managing machines out of band.
x86 boot process
Planned.
processor boot modes
Planned.
cache as ram
Planned.
dram training
Planned.
hardware description tables
Planned.
pci enumeration
Planned.
bmc out of band management
Planned.
image based provisioning
Planned.
GPUs & accelerators
How GPUs, tensor units and FPGAs execute and move data.
simt warp scheduling
Planned.
gpu memory coalescing banking
Planned.
systolic matrix units
Planned.
gpu priority preemption
Planned.
fpga dataflow pipelines
Planned.
fpga packet processing
Planned.
double buffering dma
Planned.
Chip design & EDA
Logic synthesis, placement, routing and timing for digital hardware.
arithmetic circuits
Planned.
and inverter graphs
Planned.
technology mapping
Planned.
analytical placement
Planned.
maze routing
Planned.
clock tree synthesis
Planned.
Static timing analysis
mediumPropagate latest/earliest arrival forward and required times backward through a DAG; slack = required - arrival, and the minimum-slack path is the critical one.
event driven logic simulation
Planned.
network on chip
Planned.
steiner trees
Planned.