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Hardware & OS

What the machine really does: caches, SIMD, virtual memory, the page cache, durable writes and zero-allocation I/O.

CPU

Where the nanoseconds go.

Memory

Virtual memory and mapping files.

Storage I/O

Getting bytes onto disk durably and fast.

Buffers

I/O without allocating.

Kernel mechanisms

System calls, interrupts, CPU scheduling and in-kernel extension points.

Processes & terminals

Spawning, supervising, confining and accounting for processes.

Performance analysis

Measuring where time goes on real hardware.

hardware performance counters

Planned.

sampling profiling pmu

Planned.

benchmarking methodology

Planned.

dynamic instrumentation probes

Planned.

flame graphs

Planned.

instrumented profiling

Planned.

Virtualization

Running guests: hardware virtualization, paravirtual devices, migration and snapshots.

hardware virtualization kvm

Planned.

nested paging ept

Planned.

virtio devices

Planned.

memory ballooning

Planned.

memory live migration

Planned.

dirty page tracking

Planned.

vm snapshot restore

Planned.

DMA and IOMMU

low

How devices move data by direct memory access, and how an IOMMU gives each device its own address space, faults on stray accesses and lets user space or guests own a device safely.

translate O(1) on an IOTLB hit, one table walk on a miss; unmap costs one invalidation (strict) or one per batch (lazy)

gpu virtualization

Planned.

Boot & firmware

From reset vector to running OS, and managing machines out of band.

x86 boot process

Planned.

processor boot modes

Planned.

cache as ram

Planned.

dram training

Planned.

hardware description tables

Planned.

pci enumeration

Planned.

bmc out of band management

Planned.

image based provisioning

Planned.

GPUs & accelerators

How GPUs, tensor units and FPGAs execute and move data.

simt warp scheduling

Planned.

gpu memory coalescing banking

Planned.

systolic matrix units

Planned.

gpu priority preemption

Planned.

fpga dataflow pipelines

Planned.

fpga packet processing

Planned.

double buffering dma

Planned.

Chip design & EDA

Logic synthesis, placement, routing and timing for digital hardware.

arithmetic circuits

Planned.

and inverter graphs

Planned.

technology mapping

Planned.

analytical placement

Planned.

maze routing

Planned.

clock tree synthesis

Planned.

Static timing analysis

medium

Propagate latest/earliest arrival forward and required times backward through a DAG; slack = required - arrival, and the minimum-slack path is the critical one.

O(V+E) per full run; incremental update touches only the affected fan-out and fan-in cones

event driven logic simulation

Planned.

network on chip

Planned.

steiner trees

Planned.